1. Field of Use
This invention relates to computer memories and more particularly to dual port memories.
2. Prior Art
Many processing units are required to share scratch pad memories. To avoid problems of contention in the case of simultaneous requests, it has been desirable to provide dual port read and write memories. For the most part, these memories have been constructed from separate integrated circuit chips in which access is controlled through a multiplexer circuit. This arrangement has been found to permit independent reading and writing from the input read and write ports.
Another approach has been to provide special storage cell arrangements which enable a storage location to be simultaneously read and written by employing read/write delay elements which avoid overwriting the contents of storage cells at an address which is currently selected to be read during the transition to a write at another address. While this may eliminate the use of redundant storage elements, it requires special memory cells and could also result in an increase in the overall memory cycle time. Another disadvantage of such prior art dual port read and dual port write memories is that they normally require a large number of components which take up a large area when implemented in LSI or VLSI technology. Examples of these types of arrangements are disclosed in U.S. Pat. Nos. 4,610,004 and 4,623,990.
Additionally, the prior art memories require a finite period of time in which writing is to take place. Therefore, in the case of a read modify write cycle of operation, the processing unit is required to provide the data to be stable at the memory a certain period of time before writing takes place. Since the write operation cannot take place until the modify operation is completed, the result is that additional memory cycles may be required in order to carry out the entire read modify write cycle of operation. That is, the read-modify write operation typically spans three cycles of approximately the same time duration. Therefore, when the modify operation cannot be performed within the specified time, additional cycles are required.
Therefore, it is an object of the present invention to provide a memory which has a dual port read and write capability which is implemented using standard memory cells.
It is a further object of the present invention to provide a dual read/write memory which is accessible for reading and writing from two different ports by a plurality of sources with a minimum of complexity.